patch - arm - define SYS_CACHELINE_SIZE for mx5

mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for
adding gadget support to usbarmory, but it's a property common the the
entire SoC family - may as well make it available to all MX5 boards

Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too

Signed-off-by: Chris Kuethe <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Matthew Starr <[email protected]>
Cc: Andrej Rosano <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Chris Kuethe <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index f059d0f664b35b4f5630347cdffeb60c56194efb..5f0e1e63467589b56a2360dc4c2ced246591b6f0 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -9,6 +9,8 @@
 
 #define ARCH_MXC
 
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_SOC_BASE_ADDR      0x40000000